IBM XL Compilers: Latest Power7 and Blue Gene/Q Features

Yaoqing Gao, Kit Barton, Amy Wang, Ettore Tiotto
IBM Toronto Compiler Team

Final Agenda – May 15, 2012

Morning – Power7
Presenter: Kit Barton

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1. Overview of XL compiler family
1.1 XL compiler infrastructure
1.2 Compiler releases and major features
2. Performance controls
2.1 Compiler options and flags
2.2 Compiler pragmas and directives
4. Hot spot and bottleneck detection with XL compilers
and performance tools (optional)
5. C++ specific optimization (optional)
6. Performance tuning on POWER7
6.1 POWER7 exploitation
6.2 Parallelization
6.3 Data prefetch and reorganization
6.4 Vectorization
6.5 SIMDization with VMS/VSX

Afternoon Part 1 – Blue Gene
Presenter: Amy Wang

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7. Performance tuning on BlueGene/Q
7.1 BlueGene exploitation
7.2 SIMDization with QPX
7.3 Vectorization
7.4 Parallelization
7.4.1 L2 atomic Operations and Fast wake-up support
7.4.2 Transitional Memory
7.4.3 Speculative Execution
7.5 L1P utilization
8. Summary

Afternoon Part 2 – UPC
Presenter: Ettore Tiotto

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The Partitioned Global Address Space (PGAS) programming language is a high-productivity programming model for parallel programming. PGAS languages, such as Unified Parallel C (UPC) combine the simplicity of shared-memory programming with the efficiency of the message-passing paradigm.

In this tutorial we shall present our experience in developing the IBM’s XLUPC compiler on the latest IBM’s POWER architecture. We will introduce the UPC programming model, and teach attendees how to quickly exploit the power of the language. We will also give an in depth overview of the extensive UPC specific compiler optimization infrastructure we have developed. The expected outcome is that programmers will be able to gain a better understanding of parallel programming, and code their UPC parallel applications such that performance optimization opportunities are exposed and exploited.