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The Argonne Leadership Computing Facility’s next generation machine, Mira, will be a 48-rack Blue Gene/Q with a peak performance of 10 petaflops. This talk will provide an update on the system installation, efforts to test for acceptance, and other preparation for a fully operational environment. In addition, the Early Science Program has enabled users from a variety of projects to access early system hardware and many codes are already up and running on the BG/Q with promising results.

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Eclipse PTP is an open source project built on the phenomenally successful Eclipse platform,  that aims to improve the tools that are available for developers of parallel and scientific applications. PTP includes support for C, C++, UPC, and Fortran, as well as static analysis tools for MPI, OpenMP and UPC programming models, support for a wide variety of job schedulers and parallel systems, an integrated parallel debugger, and much more. In this demo, we will give a brief introduction to using Eclipse PTP for developing parallel applications, and show some of the new features that will be available in the upcoming “Juno” release in June 2012.

Date: Wednesday, May 16, 2012
Time: 18:00-20:30

180 Panorama is about 1 mile / 1.6 km (~20 minute walk) from the Delta Chelsea.

• Walking: Google Maps – route to 180 Panorama from the Delta Chelsea
• Or via subway + shorter walk: take subway from College Station to the Bloor-Yonge Station via the Yonge-University-Spadina line.   [Subway map]
• If you drive, parking locations are indicated on the detail map below.

The best entrance to get to Panorama in the Manulife Centre is near Bay and Charles streets. The check in/entrance at the south side of the Manulife Centre on the 2nd floor right next to the Varsity Cinema ticket booths. Panorama is on the 51st floor. The Manulife Centre’s address is 55 Bloor Street West.

Panorama 180 – Location Detail Map

Note: The SPXXL/ScicomP private party ends at 20:30 but you can stay later if you like since Panorama 180 is open to the public afterwards.

Presented by Giri Prabhakar, IBM India, STG

Intel Sandy Bridge support a new set of instructions called as AVX which is the extended capability of (i) Streaming SIMD Extension (SSE) and (ii) MultiMedia eXtension (MMX) especially for floating point data and operations. There are lots more changes happened in micro-architecture level compared with usual SSE instruction to improve the application performance. Some of the modifications are, 128 bit SSE registers into 256 bits (as a doubling the registers), new instruction encoding mechanism like 2 operand to 3 operand instructions etc. Even though, the new encoding technique is common for 128 bit AVX instructions which can use older SSE instructions there by no more source code modification required and the application performance may be improved by using new encoding mechanism Some of the application may not take this advantages even though we compiled the source code with AVX options. Therefore, in order to improve the performance, need to ensure (i) AVX supported version of compilers, the appropriate options in the compiler flags & its corresponding assembly language related to AVX instructions (ii) identify the possibilities of performance gap or optimal way of registers used in the AVX instructions by the way of hand tuning etc. Here, I demonstrated those performance improvement options using molecular dynamics application. For example, even though GNU complier 4.5.x version supported for extended SSE instruction features (like AVX instructions & its 256 bit registers), the application performance may not be improved due to compiler may not generate AVX macro instructions. Alternatively, GNU compiler 4.7.x supported appropriate AVX instructions for Intel Core i7 Sandy Bridge processor and we were able to improve the performance up to 23% (18% from AVX instruction support from the compiler and 5% by modifying the source code). We compared the performance variation by (i) hybrid options by increase/decrease the number of OMP threads (ii) compute & communication ratio and (iii) call graph and its execution time across various subroutines etc. between Westmere and Sandy Bride was demonstrated.

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The current and expected explosive growth in the availability of shared-memory concurrency greatly increases the burden on the programmer to effectively utilize the large number of cores and even larger number of threads.  One of the main challenges of writing thread-safe code, however, has been the efficient resolution of memory conflicts. Transactional memory (TM) offers all of the attributes of thread-safety, but in a cost-effective and scalable manner.  It is an optimistic synchronization mechanism in thata memory update is allowed to go through without locks, but checked afterwards whether or not a conflict has occurred.  If a conflict was indeed detected, a “rollback” ensues and the memory commit is typically retried a preset number of times, before it becomes serialized.  When TM is implemented in hardware using a multi-versioned L2 cache, such as in the IBM Blue Gene/Q (BG/Q) systems, this method can become very efficient, especially for low memory contention applications.

In this work, we present very recent results using IBM’s hardware transactional memory (HTM) system.  To demonstrate the utility of TM in the scientific computing world, we have built a benchmark code that intends to mimic the algorithms and code behavior of some very large scientific simulations.  Our particular code is named BUSTM (Benchmark for UnStructured-mesh Transactional Memory) because it uses real 3-D unstructured grids and it contains two frequently used algorithms which have very low, but nonzero memory conflict probabilities.  One is the conservative finite volume method often used in CFD (Computational Fluid Dynamics) simulations, and the other is the Monte-Carlo method for particle transport.

In our experiments we analyze the memory access and conflict patterns of both algorithms included in BUSTM as well as compare the number of rollbacks to the number of wrong answers obtained without synchronization.  Our results confirm the low-conflict property of the numerical methods presented, thereby indicating a good fit between these application scenarios and the TM features. Finally, our experiments also demonstrate clear performance advantages when compared to more traditional thread synchronization mechanisms, such as OpenMP “critical,” and, in certain cases, even “atomic.”

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David Wootton and John Robb
High Performance Computing, Systems and Technology Group, IBM Poughkeepsie, USA

Presented by Greg Watson, IBM Watson, STG

In this presentation we will highlight the new features of scalable IBM HPC toolkit available for Power 7 and x86 (Intel Sandy Bridge) architecture. The presentation will consists of three parts. In the first part of our presentation we will be talking about some challenges in developing scalable performance monitoring tools for application developers. The primary objective of developing such scalable tools on the emerging peta- and exa-scale high performance computing systems is to provide a common, light-weight, portable and extensible run-time and scalable communication framework. In addition to that, such tools should also be designed in such a way that it meets the PERCS (Programmable Easy-to-use Reliable Computing System) standard. To fulfill such requirements, the scalable IBM HPC toolkit deploys a multitask/reduction network based on SCI (Scalable Communication Infrastructure) framework [SCI]. In our presentation we will discuss the SCI based scaling model used in IBM HPC toolkit which is capable of doing performance analysis of large scale applications.

In the second part of our presentation we will be talking about the new features available in the toolkit for the PERCS interconnect, namely HFI. IBM Host Fabric Interface (HFI) [HFI-1] is a new cluster interconnection network device designed for the high end Power7 based supercomputers (IBM Power 775) and is specially designed for large scale cluster computing. HFI enables the user to have performance boost for collective operations which requires a subset of all processes participating in a parallel job to wait for a result whose value depends on one or more input values provided by each of the participating processes. In HFI, the collective acceleration unit (CAU) controls the implementation of the collective operations (collectives). In this part of our presentation we will be discussing about different hardware performance counter groups used in IBM HPC Toolkit to measure the hardware performance of an application which uses HFI and CAU units.

The last part of our presentation will focus on the new features of IBM HPC toolkit for x86 (Intel Sandy Bridge) platform. We will high light the new hardware counters available for Sandy Bridge processor and related hardware performance analysis in this newly introduced family of x86 architecture.

References

[1] Scalable Communications Infrastructure : URL : http://wiki.eclipse.org/PTP/designs/SCI

[2] B. Arimili et al, The PERCS High-Performance Interconnect, 18th IEEE Symposium on High Performance Interconnects, 2010, URL : http://www.unixer.de/publications/img/ibm-percs-network.pdf

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* presenting author

Increasing sophistication in HPC system architectures, software stack, and user environments have increased the complexity of HPC application deployment for the end user.  For example, tuning an application on a given platform to maximize performance requires exploring combinations of multitude of different optimization flags and environment variables.  Similarly, there may be a number of different HPC applications run by different customers on the same platform, each with their specific system
and application settings.

In these scenarios, users are required to create a complex stack of scripts for the deployment of jobs with their specific settings.  In each separate instance, the application deployment process results in users creating a customized stack of scripts for that instance.  This results in the creation of many sets of similar stacks of scripts  for each specific instance.  Creation and management of the growing set of scripts and test configurations is a non-trivial task that consumes a significant amount of productive resources.

As the sets of scripts grow over time, tracking and book-keeping of the details of each application deployment instance also becomes increasingly tedious.  For example, which configuration settings had given optimal results last month for application X can pose a very tedious process of going through multiple directory trees to find the right data/scripts.  In complex execution instances, there may be many sets of data generated for each parameter combination, and sifting through the data also becomes difficult.

This talk presents Job Auto-Creation and Executor (JACE), a tool that provides a user interface designed to automate the creation and execution of HPC jobs that require deployment over a complex set of configuration parameters.  The tool aims to address many pain points described above such as: automating the tedious and repetitive scripting process, setting up parameter-sweep experiments automatically, and careful book-keeping of each deployment instance.  Simply put, JACE automates HPC job configuration management for the user and has following features:

• Assists and automates generation of complex combinations of job settings by enabling users to specify configuration parameters using standard forms.
• Automates generation of a stack of scripts for complex parameter sweeps without requiring any additional scripting from the user.  This enables users to try multiple values for an an application parameter by means of only modifying the parameter values (or ranges) in the job form.  Users may also specify conditional values that are effective depending on the value of a set of parameters.
• Job forms are easily created by inheriting from a ‘stencil’ form, which is the template representative of the application-platform combination.  Once created, a job may be run repeatedly in a ‘turnkey’ fashion, and each such instance is automatically managed separately.
• Book-keeping for jobs (job forms, scripts, configuration parameters and other notes) is automatically managed, with the user required only to enter notes for their reference.  Job management databases are searchable and jobs are re-runnable.

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